1. Field of the Invention
The present invention relates to hardware design. In particular, the invention relates to a re-configurable hardware design implemented in the integrated circuit (IC) of a wireless communication device.
2. Description of the Prior Art
Integrated circuits have improved so much that most signal processing is now performed in ICs rather than in discrete circuits. When an IC chip is mass produced in large quantities, the cost per individual IC chip is exceptionally low. Other advantages of modern ICs are their high element density and low power consumption. These advantages have led to a proliferation of small and relatively inexpensive wireless communication devices in the last decade.
Silicon transistors, both bipolar and complementary metal-oxide semiconductor (CMOS) types, are now so fast that radio frequency (RF) circuits in the lower GHz range can be provided in the IC of a wireless communication device. This has lead to significant improvements in the capabilities of modern wireless communication devices. Such devices include, but are not limited to, mobile phones, personal digital assistants, handheld computers, etc.
A familiar consideration in the design of IC chips is that they must have enough flexibility to be used in several different products and, in the case of wireless communication devices, to allow for future upgrades or evolutions in standards. Although software defined radio (SDR) design has been discussed much recently, software implementation of the complex algorithms necessary for communications typically requires a large amount of clock cycles of a digital signal processor (DSP). As a result, such designs cannot provide the higher performance necessary, for example, to support real-time multimedia services of third generation (3G) wireless communications systems. Various tradeoffs involved when writing software algorithms are discussed in the article entitled “Division and Square Root—Choosing the Right Implementation”, by Peter Soderquist et al, IEEE Micro, pages 56–66, July/August 1997.
Conventional re-configurable hardware designs are known, typically consisting of either a field programmable gate array (FPGA) or an array of computing elements. Each design has unique advantages and disadvantages. For example, a FPGA has high programmability but typically has low calculation speed due to routing delays. An array of computing elements has high computational speed but usually a low degree of utilization due to the functional level of programmability.
A recent article entitled “CDSP: An Application Specific Digital Signal Processor for Third Generation Wireless Communications” by Po-Chih Tseng et al, IEEE 2001, describes a programmable digital signal processor (DSP) design proposed specifically for 3G wireless communications. See FIG. 1. Although the design has an architecture and instruction set specially designed for the Wideband Code Division Multiplex Access (WCDMA) radio interface of a communications system, it still suffers the latencies resulting from basic arithmetic operations like square root and division.